Rataser - FPGA firmware for clock, signal and trigger distribution

General Information

Rataser is a collection of unidirectional single-wire signal transmission protocols, suitable for use over various (dispersion) qualities of cables and fibres. The implementation of the sender and receiver functions is in generic VHDL. The protocols support clock and time distribution (rataclock), general signal distribution (ratasig), and (to-finalise) trigger distribution.

Type
Special-purpose firmware and software.
Language
Firmware: VHDL.
License
Rataser is free software; distributed under the 3-clause BSD license.
See the accompanying LICENSE file.
Performance
Rataclock: PLL clock recover < 100 ps. In time-only mode: better than 2 receiver clock cycles.
Rataser: > 150 Mbaud.
Main developers
Håkan T. Johansson, Chalmers University of Technology, Sweden. Hardware implementation and tests: Bastian Löher, GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt, Germany.
Distributor
Experimental subatomic physics group, Chalmers University of Technology, Sweden.
Acknowledgment
The research leading to these results was supported by the Swedish Research Council: the Scientific Council for Natural and Engineering Sciences under grant 2017-03839 and the Council for Research infrastructure under grant 822-2014-6644.

Download

Location
http://fy.chalmers.se/~f96hajo/rataser/rataser-20220608.tar.gz
Contact
Håkan T. Johansson (f96hajo@chalmers.se)
Version
20220608 (CHANGELOG)
Support
No formal support.

Documentation

See README (included with download).

Rataclock simulation screenshots.

Interfaces (FPGA modules in VHDL)

Rataclock sender
The interface to send a rataclock signal.
The transmission is based on the local clock, and a continously updating timestamp register. 
entity rataser_clock_send is
    generic (period_bits:        integer
             );
    port (clk:               in  std_logic;
          -- Input timestamp information, and auxilliary signals.
          tick_ns:           in  std_logic_vector(63 downto 0);
          aux_sigs:          in  std_logic_vector(4 downto 0);
          info_bit:          in  std_logic;
          -- Rataclock signal parameters.
          pulse_period_clks: in  std_logic_vector(period_bits-1 downto 0);
          duty_low_min_clks: in  std_logic_vector(period_bits-1 downto 0);
          duty_low_max_clks: in  std_logic_vector(period_bits-1 downto 0);
          eight_slot:        in  std_logic;
          -- Clock and (optional) latency information.
          pulse_period_ns:   in  std_logic_vector(9 downto 0);
          message_delay_ns:  in  std_logic_vector(21 downto 0);
          -- The rataclock signal (with oscilloscope debug mark).
          transmit:          out std_logic;
          transmit_sync:     out std_logic
          );
end;
Rataclock receiver
The interface to receive a rataclock signal.
Note that the protocol can be used to distribute a clock signal (eight_slot-mode), where the local clk and clk90 signals are derived from a PLL driven by the rataclock signal.
In time-only mode, clk can be any local clock signal, and clk90 is not needed. 
entity rataser_clock_recv is
    generic(period_bits: integer;
            num_last_edges: integer;
            max_skew_4phase_sample: string
            );
    port (clk:               in  std_logic;
          clk90:             in  std_logic;
          -- The rataclock signal.
          receive:           in  std_logic;
          eight_slot:        in  std_logic;
          -- Resolving phase in clock-mode.
          expect_edge:       in  std_logic_vector(1 downto 0);
          last_edges:        out std_logic_vector(num_last_edges*2-1 downto 0);
          use_auto_edge:     in  std_logic;
          auto_edge:         out std_logic_vector(1 downto 0);
          -- (Optional) latency information.
          receive_delay_ns:  in  std_logic_vector(15 downto 0);
          -- Output timestamp, and auxilliary signals.
          tick_ns_lo:        out std_logic_vector(31 downto  0);
          tick_ns_hi:        out std_logic_vector(63 downto 32);
          aux_sigs:          out std_logic_vector(4 downto 0);
          info_bit:          out std_logic;
          msg_strobe:        out std_logic;
          -- Synchronisation status.
          sync_status:       out std_logic_vector(2 downto 0);
          sync_lost:         out std_logic_vector(2 downto 0);
          bad_signals:       out std_logic_vector(4 downto 0);
          clear_status:      in  std_logic;
          -- Clock information in clock-mode.
          pulse_period_clks: in  std_logic_vector(period_bits-1 downto 0);
          clk_period_ns:     in  std_logic_vector(9 downto 0);
          );
end;
Ratasig sender
Transmission of 1 or 4 signals (multiplexed) over a single wire or optical fibre. 
entity rataser_signals_send is
    port (clk:           in std_logic;
          -- Input signals (only index 0 if single_symbol_mode).
          signals:       in std_logic_vector(3 downto 0);
          -- Auxiliary information.
          info_bit:      in std_logic;
          -- Transmission mode (1 or 4 signals).
          single_symbol_mode: in std_logic;
          -- Output serial signal (with oscilloscope debug mark).
          transmit:      out std_logic := '0';
          transmit_sync: out std_logic := '0'
          );
end;
Ratasig receiver
Receive 1 or 4 signals. 
entity rataser_signals_recv is
  port (fast_clk:      in std_logic;
        fast_clk90:    in std_logic;
        -- Input serial signal.
        receive:       in std_logic;
        -- Output signals (only 0 if single_symbol_mode).
        signals:       out std_logic_vector(3 downto 0);
        -- Auxiliary information.
        info_bit:      out std_logic;
        -- Strobe signal.
        msg_strobe:    out std_logic;
        -- Transmission mode.
        single_symbol_mode: in std_logic;
        -- Counter of bad bits.
        bad_bit_count: out std_logic_vector
        );
end;
Comments? f96hajo@chalmers.se

Last modified: Tue 22 Mar 2022 08:45:03 CET 2022