TRLO II firmwares (fb441ca)

The firmware images come with ABSOLUTELY NO WARRANTY!

Download: trloii_firmwares_fb441ca.tar.gz

Contents:

File md5sum Min period git describe Created
vulom4_trlo/vlogic_1.rbt6ddd55e434f285112c2b9004d15175e59.496nsfb441ca2016-01-17
vulom4b_trlo/vlogic_4b.rbtb2056bdd052a36200a6e7a7bcc63e7299.482nsfb441ca2016-01-17
vulom4_trlo_all_in/vlogic_1.rbt39253d2e3ddd7b99e513d1329b27a3e19.500nsfb441ca2016-01-17
vulom4_trlo_big/vlogic_1.rbt8cb0d706c336e2d53e4aba9aa616a35d9.481nsfb441ca2016-01-17
tridi1_trlo/tlogic_1.rbta1d65a3c656ecb84ccfa78a4a2064ad39.493nsfb441ca2016-01-17
vulom4_trlo_led/vlogic_1.rbt7c59f4da54035ec1ceb0ec3b6cfeb6fe9.494nsfb441ca2016-01-17

With the VULOM/TRIDI FPGA operated at 100 MHz, the compile timing constraint of 9.5 ns gives some slight margin for fixes.

Main changes:

2016-01-17:
Introduced Heimtime (speaking clock) sender.
Removed PRNG_LFSR, expected to not have been used.
Removed RANDOM_TCAL, no usage reported.

2015-06-23:
Ensure master start is followed by accept pulse, even on sudden DT or busy.

2014-07-26:
Avoid lock-up of the serial receiver due to DSP underflow.

2014-06-26:
Slew counter to control sent serial time stamp.

2014-05-12:
Advisory (soft) DT input for the TRIMI, for use with timestamped slaves.

2014-03-30:
Do not wait for (remote) DT release when not using the link,
Use DSP blocks for pattern latches and some gate stretchers.

2014-02-12:
Inverted & flipped VULOM4B LEMO in/out,
Missing scaler for last trigger LMU out after reduction,
TRIMI DT mon,
TRIMI dt in clear only after a few repeated zero cycles,
half-speed scalers for leading-edge counters (signals come at most every second cycle).

2014-01-11:
Major update.