TRLO II firmwares (c44f109)

The firmware images come with ABSOLUTELY NO WARRANTY!

Download: trloii_firmwares_c44f109.tar.gz

Contents:

File md5sum Min period git describe Created
vulom4b_trlo/vlogic_4b.rbtb25d9c4b09502cd352013540426cb99c9.486nsc44f1092018-10-07
tridi1_trlo/tlogic_1.rbt1a902d838f9184d824a40955d374466d9.492nsc44f1092018-10-07
vulom4_trlo_all_in/vlogic_1.rbt3bfa8ccdb51a8a1a0511a49c5b2981659.492nsc44f1092018-10-07
vulom4_trlo/vlogic_1.rbt4e9aed3b341ff25fabfe07cbd96ffc889.497nsc44f1092018-10-07
vulom4_trlo_big/vlogic_1.rbtd5a61f258416547a55764c366f28c0f89.479nsc44f1092018-10-07
vulom4_trlo_led/vlogic_1.rbta886f656eb8e1eeba12bf990fa5020ea9.496nsc44f1092018-10-07

With the VULOM/TRIDI FPGA operated at 100 MHz, the compile timing constraint of 9.5 ns gives some slight margin for fixes.

Main changes:

2018-10-07:
Multi-event scalers.
Toggle-mode busy handling.
Repair TRIMI link master start count.

2018-04-15:
Poisson pulser driven by xorshift PRNG.
(Removed one pulser unit.)

2018-03-08:
TRIMI only wait for DT send timeout if having slaves.
More bits for the multi-event counter.

2016-01-17:
Introduced Heimtime (speaking clock) sender.
Removed PRNG_LFSR, expected to not have been used.
Removed RANDOM_TCAL, no usage reported.

2015-06-23:
Ensure master start is followed by accept pulse, even on sudden DT or busy.

2014-07-26:
Avoid lock-up of the serial receiver due to DSP underflow.

2014-06-26:
Slew counter to control sent serial time stamp.

2014-05-12:
Advisory (soft) DT input for the TRIMI, for use with timestamped slaves.

2014-03-30:
Do not wait for (remote) DT release when not using the link,
Use DSP blocks for pattern latches and some gate stretchers.

2014-02-12:
Inverted & flipped VULOM4B LEMO in/out,
Missing scaler for last trigger LMU out after reduction,
TRIMI DT mon,
TRIMI dt in clear only after a few repeated zero cycles,
half-speed scalers for leading-edge counters (signals come at most every second cycle).

2014-01-11:
Major update.