TRLO II firmwares (1cd8e53)

The firmware images come with ABSOLUTELY NO WARRANTY!

Download: trloii_firmwares_1cd8e53.tar.gz

Contents:

File md5sum Min period git describe Created
vulom4b_trlo/vlogic_4b.rbtd5fa1ec5dcdcf274a97eae3ada74fc989.500ns1cd8e532018-06-06
tridi1_trlo/tlogic_1.rbt9c33b050fc3248afcb34ca2dcf55c11e9.498ns1cd8e532018-06-06
vulom4_trlo_all_in/vlogic_1.rbt95091b5d444606f05bd1c0adf10cc1bd9.500ns1cd8e532018-06-06
vulom4_trlo/vlogic_1.rbt6ee93c7ebd595820b54c876e90a1caf09.490ns1cd8e532018-06-06
vulom4_trlo_big/vlogic_1.rbt45e8ab0039022ee511a8d65b1af9949b9.493ns1cd8e532018-06-06
vulom4_trlo_led/vlogic_1.rbt8c3b5c95bca7addff5b3ab5976e15e909.498ns1cd8e532018-06-06

With the VULOM/TRIDI FPGA operated at 100 MHz, the compile timing constraint of 9.5 ns gives some slight margin for fixes.

Main changes:

2018-04-15:
Poisson pulser driven by xorshift PRNG.
(Removed one pulser unit.)

2018-03-08:
TRIMI only wait for DT send timeout if having slaves.
More bits for the multi-event counter.

2016-01-17:
Introduced Heimtime (speaking clock) sender.
Removed PRNG_LFSR, expected to not have been used.
Removed RANDOM_TCAL, no usage reported.

2015-06-23:
Ensure master start is followed by accept pulse, even on sudden DT or busy.

2014-07-26:
Avoid lock-up of the serial receiver due to DSP underflow.

2014-06-26:
Slew counter to control sent serial time stamp.

2014-05-12:
Advisory (soft) DT input for the TRIMI, for use with timestamped slaves.

2014-03-30:
Do not wait for (remote) DT release when not using the link,
Use DSP blocks for pattern latches and some gate stretchers.

2014-02-12:
Inverted & flipped VULOM4B LEMO in/out,
Missing scaler for last trigger LMU out after reduction,
TRIMI DT mon,
TRIMI dt in clear only after a few repeated zero cycles,
half-speed scalers for leading-edge counters (signals come at most every second cycle).

2014-01-11:
Major update.