The firmware images come with ABSOLUTELY NO WARRANTY!
Download: trloii_firmwares_f13d071c.tar.gz
Contents:
| File | md5sum | Min period | git describe | Created |
|---|---|---|---|---|
| vulom4_trlo/vlogic_1.rbt | d3a297d88f959d3d2854e2d86e4ba1a9 | 9.491ns | f13d071c | 2023-01-08 |
| vulom4_trlo_led/vlogic_1.rbt | b4eeff3d33e3176a00d9b940a73c5093 | 9.500ns | f13d071c | 2023-01-08 |
| vulom4_trlo_big/vlogic_1.rbt | da447297e0a3b70ca4ba100daf33ed35 | 9.477ns | f13d071c | 2023-01-08 |
| tridi1_trlo/tlogic_1.rbt | adcccfee09155c3bd26740155e8f5ef4 | 9.491ns | f13d071c | 2023-01-08 |
| vulom4b_trlo/vlogic_4b.rbt | 50bd8004b6f94bec831440791409285e | 9.499ns | f13d071c | 2023-01-08 |
| vulom4_trlo_all_in/vlogic_1.rbt | 4aaa2604d36bd2f45ce1d54168f8955e | 9.477ns | f13d071c | 2023-01-08 |
With the VULOM/TRIDI FPGA operated at 100 MHz, the compile timing constraint of 9.5 ns gives some slight margin for fixes.
Main changes:
2023-01-08:
Repair VME read with V17 controller.
Avoid overflow/wrap for variable master start length.
2022-02-17:
Optional variable (event count+random) master start length.
Measure signal length for sync check.
(Two more front-panel LEDs fixed.)
2020-07-15:
Delay read after write of scaler latch (would-be issue with fast VME controllers).
2018-10-07:
Multi-event scalers.
Toggle-mode busy handling.
Repair TRIMI link master start count.
2018-04-15:
Poisson pulser driven by xorshift PRNG.
(Removed one pulser unit.)
2018-03-08:
TRIMI only wait for DT send timeout if having slaves.
More bits for the multi-event counter.
2016-01-17:
Introduced Heimtime (speaking clock) sender.
Removed PRNG_LFSR, expected to not have been used.
Removed RANDOM_TCAL, no usage reported.
2015-06-23:
Ensure master start is followed by accept pulse, even on sudden DT or busy.
2014-07-26:
Avoid lock-up of the serial receiver due to DSP underflow.
2014-06-26:
Slew counter to control sent serial time stamp.
2014-05-12:
Advisory (soft) DT input for the TRIMI, for use with timestamped slaves.
2014-03-30:
Do not wait for (remote) DT release when not using the link,
Use DSP blocks for pattern latches and some gate stretchers.
2014-02-12:
Inverted & flipped VULOM4B LEMO in/out,
Missing scaler for last trigger LMU out after reduction,
TRIMI DT mon,
TRIMI dt in clear only after a few repeated zero cycles,
half-speed scalers for leading-edge counters (signals come at most every second cycle).
2014-01-11:
Major update.