TRLO II firmwares (231939f)

The firmware images come with ABSOLUTELY NO WARRANTY!

Download: trloii_firmwares_231939f.tar.gz

Contents:

File md5sum Min period git describe Created
vulom4b_trlo/vlogic_4b.rbt42ba6c042fa1a3d96aaa35d71c0390fa9.499ns231939f2018-04-15
tridi1_trlo/tlogic_1.rbtf140e08dce2d511f5c1753e3bd74b80d9.498ns231939f2018-04-15
vulom4_trlo_all_in/vlogic_1.rbtf2d2e307dc04ae7090b0de63ac5cee569.492ns231939f2018-04-15
vulom4_trlo/vlogic_1.rbt2dc43f8d969bc0420874a4996ea4dfb19.492ns231939f2018-04-15
vulom4_trlo_big/vlogic_1.rbt721d8876037e1d0316b7f4934b2da9b59.495ns231939f2018-04-15
vulom4_trlo_led/vlogic_1.rbtec69c5b6449c96a33fb4b99ac4649bd39.488ns231939f2018-04-15

With the VULOM/TRIDI FPGA operated at 100 MHz, the compile timing constraint of 9.5 ns gives some slight margin for fixes.

Main changes:

2018-04-15:
Poisson pulser driven by xorshift PRNG.
(Removed one pulser unit.)

2018-03-08:
TRIMI only wait for DT send timeout if having slaves.
More bits for the multi-event counter.

2016-01-17:
Introduced Heimtime (speaking clock) sender.
Removed PRNG_LFSR, expected to not have been used.
Removed RANDOM_TCAL, no usage reported.

2015-06-23:
Ensure master start is followed by accept pulse, even on sudden DT or busy.

2014-07-26:
Avoid lock-up of the serial receiver due to DSP underflow.

2014-06-26:
Slew counter to control sent serial time stamp.

2014-05-12:
Advisory (soft) DT input for the TRIMI, for use with timestamped slaves.

2014-03-30:
Do not wait for (remote) DT release when not using the link,
Use DSP blocks for pattern latches and some gate stretchers.

2014-02-12:
Inverted & flipped VULOM4B LEMO in/out,
Missing scaler for last trigger LMU out after reduction,
TRIMI DT mon,
TRIMI dt in clear only after a few repeated zero cycles,
half-speed scalers for leading-edge counters (signals come at most every second cycle).

2014-01-11:
Major update.