WP 1. Fabrication of qubit circuitry and instrumentation

Lead contractor: PTB

Participants: Chalmers, HUT, KTH, TU Delft, CEA-Saclay, JyU

WP 1 deals with basic issues of fabrication of charge, flux and hybrid qubits using Josephson junction (JJ) circuits (single Cooper pair boxes for charge qubits, SQUID loops for flux qubits, and a Cooper pair transistor in a SQUID loop for the hybrid qubit; we will also investigate how to make JJ arrays for topologically protected qubits). A major effort will be devoted to designing and fabricating coupled qubit circuits with fixed and, if possible, switchable qubit-qubit coupling.

The major effort of the collaboration will be focused on fabricating systems of quantum logic gates by developing the Josephson junction technology for charge-phase and flux qubits, as well as combining Josephson junction, single-electronics (RF-SET) and SQUID technologies for achieving fast readout of qubit information. A Superconducting Cooper pair transistor (SCPT) in a superconducting loop configuration forms the basic qubit, in principle spanning the entire range from charge to flux qubits. Since the pure charge qubit is very sensitive to charge noise, the research within the consortium will be focused on the charge-phase and flux qubits for single-qubit and multi-qubit implementations.