The firmware images come with ABSOLUTELY NO WARRANTY!
Download: trloii_firmwares_40064ade.tar.gz
Contents:
File | md5sum | Min period | git describe | Created |
---|---|---|---|---|
vulom4_trlo/vlogic_1.rbt | b14512a675b02e627225cec5fcb4e72c | 9.474ns | 40064ade | 2024-05-15 |
vulom4_trlo_led/vlogic_1.rbt | 0b3b3a74aa3ce9c270b9ede0a45a99ee | 9.490ns | 40064ade | 2024-05-15 |
vulom4_trlo_big/vlogic_1.rbt | 3b5605db5915ef4be611811ca50005c1 | 9.472ns | 40064ade | 2024-05-15 |
tridi1_trlo/tlogic_1.rbt | bb5550140e83fa0c8004c861f5bbfa96 | 9.500ns | 40064ade | 2024-05-15 |
vulom4b_trlo/vlogic_4b.rbt | 7517d22a593ae2462ba072f43b935cc3 | 9.500ns | 40064ade | 2024-05-15 |
vulom4_trlo_all_in/vlogic_1.rbt | 183bc6357942af6a19f90d417e5a6639 | 9.500ns | 40064ade | 2024-05-15 |
With the VULOM/TRIDI FPGA operated at 100 MHz, the compile timing constraint of 9.5 ns gives some slight margin for fixes.
Main changes:
2024-05-15:
Pending triggers marked as prompt are non-pending; only trigger if idle.
Initialize mux registers as wired_zero on startup.
2023-01-08:
Repair VME read with V2718 controller.
Avoid overflow/wrap for variable master start length.
2022-02-17:
Optional variable (event count+random) master start length.
Measure signal length for sync check.
(Two more front-panel LEDs fixed.)
2020-07-15:
Delay read after write of scaler latch (would-be issue with fast VME controllers).
2018-10-07:
Multi-event scalers.
Toggle-mode busy handling.
Repair TRIMI link master start count.
2018-04-15:
Poisson pulser driven by xorshift PRNG.
(Removed one pulser unit.)
2018-03-08:
TRIMI only wait for DT send timeout if having slaves.
More bits for the multi-event counter.
2016-01-17:
Introduced Heimtime (speaking clock) sender.
Removed PRNG_LFSR, expected to not have been used.
Removed RANDOM_TCAL, no usage reported.
2015-06-23:
Ensure master start is followed by accept pulse, even on sudden DT or busy.
2014-07-26:
Avoid lock-up of the serial receiver due to DSP underflow.
2014-06-26:
Slew counter to control sent serial time stamp.
2014-05-12:
Advisory (soft) DT input for the TRIMI, for use with timestamped slaves.
2014-03-30:
Do not wait for (remote) DT release when not using the link,
Use DSP blocks for pattern latches and some gate stretchers.
2014-02-12:
Inverted & flipped VULOM4B LEMO in/out,
Missing scaler for last trigger LMU out after reduction,
TRIMI DT mon,
TRIMI dt in clear only after a few repeated zero cycles,
half-speed scalers for leading-edge counters (signals come at most every second cycle).
2014-01-11:
Major update.