Some descriptions to help clarify the floating boundaries between electronic/logic components.
Explanations are a bit recursive - having an chicken-and-egg problem. First a short list:
| Hardware | Actual physical hardware. Difficult to change after producion - basically soldering iron. |
| Gateware | A part of the hardware design for FPGAs/CPLDs, in the form of software; can (with more or less effort) be replaced after production. |
| - Gateware image | The actual form of the gateware that can be configured on hardware. |
| Firmware | A part of the hardware design for DSPs or embedded CPUs, in the form of software; can (with more or less effort) be replaced after production. |
| - Firmware image | The actual form of the firmware that hardware can execute. ('Machine code'). |
| Software | Instructions / algorithms to be processed by hardware (ASICs). |
| - Executable file | The form of software processors can deal with - execute. ('Machine code'). |
| - Source code | The human-readable from of the software (or firmware). |
| - Portable | Software that can be compiled or synthezised for different architectures. |
| ASIC | Application specific integrated circuit - a chip! |
| - Processor | An advanced kind of ASIC - processes instructions. |
| - - CPU | (General purpose) processor. |
| - - DSP | Digital signal processor - special purpose (usually communication links or images). Runs firmware. |
| - FPGA | Field-programmable gate array, an advanced ASIC. Replaces discrete components in hardware designs. Configured with gateware |
| - CPLD | Complex programmable logic device |
| Development tools | Programs used for software engineering: |
| - Compiler | Translates (software) source code into machine code for a specific kind (architecture) of CPU or DSP. |
| - Linker | Combines object files of machine code into an executable program. |
| - Synthesizer | Translates (firmware) source code into logic elements available in a specific kind (architecture) of FPGA or CPLD. |
| - Map / place & route | Assigns specific logic elements and signal routing to actual elements in a particular kind (size, speed-grade) of FPGA. |