In Fig. 5-1 our amplifiers noise is compared with data taken from ref. [5] . The 1/f noise performance is superior to Lee's amplifier, while the thermal noise floor seems equal. The former was expected since the MESFETs where designed with a large gate area to lower the 1/f noise [8] .
5.2 Improving the Performance
Lee achieved a spot noise level at 1 MHz of 0.9 nV/(Hz)½ at 4.2 K 0 [5] . This is not directly comparable to our spot noise at 100 kHz since the noise spectrum still drops off at 100 kHz. The spot noise at 1 MHz remains to be examined.
The noise minimum is in the upper left corner of the bias map and there is a possibility that even lower noise levels can be reached at larger drain currents and lower drain source voltages. This has to be checked.
The equivalent input noise current has to be measured and plotted in a bias map. Together with the equivalent noise voltage measured in this work it will then be possible to find the optimum resistance of a signal source yielding lowest noise.
The noise contribution of the JFET Q2 has to be measured. It may be possible to lower noise levels by replacing the JFET with a low-noise bipolar transistor, although it has been shown that the input stage of the cascode is the dominant noise source [9] .
The gain of the cascode is about 22.5 at the bias point with lowest noise, which is almost five times larger than in Lee's. The much larger gate area of the MESFET used in our cascode controls a wider channel and the transconductance is therefore greater than in the small gate FETs used by Lee [5] . The gain is set by the JFET drain resistor and must be lowered 5 times to about 400 ohm to get a gain of five. This decreases the output impedance of the cascode and will probably raise the bandwidth (see below).
The lower frequency corner is about 400 Hz at lowest noise and is set by two RC time constants, the MESFET source AC-ground and the JFET gate AC-ground. The first one consist of the source trimmer in parallel with a capacitor. The second one consists of the gate trimmer network in parallel with a capacitor and in series with the source-gate resistance of the JFET. Both are bias dependent but can be arbitrarily low by increasing the capacitor values. The upper frequency cut-off is about 700 kHz which is 14 times lower than the 10 MHz achieved by Lee[ 5]. The dip in the gain at 700 kHz lowers the bandwidth and the origin of this effect is unknown. If the dip is removed and a simple high-pass filter response is extrapolated, the frequency corner will be found near 2 MHz. The main RC time constant is formed by the capacitance from the coaxial cable to ground in the dipstick, giving a total of about 100 pF, and the source to gate input resistance of the JFET of some 200-300 ohm, yielding a cut off frequency of 6 MHz. The op-amp stages also contribute due to their gain-bandwidth product. With the dip removed at 700 kHz, the amplifier would have a gain-bandwidth product of 50 MHz which is the same as Lee found [5] . Decreasing the gain by a factor of five should increase the bandwidth to 10 MHz.
The cascode is susceptible to resonance with the power supply filters. This can be reduced by inserting a small resistor in series with the source biasing network. The resistor will provide negative feedback to the gate mirroring the fluctuations in the drain current. However, this will also decrease the gain. An alternative is to replace the entire source network with an active current source. This may however increase the noise.